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Memory Timings Explained
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Registered The Athlon64 boards out right now require registered memory. What is this? Registered memory is slightly different than ECC memory. Most registered memory HAS ECC but to be a registered DIMM doesn't always mean that it has ECC. The registered part of the memory acts like a buffer it basically guides the data to the appropriate place. It was designed to give assistance when massive amounts of data are being transferred. Common in high end workstations and servers. If you're going this high end you better make sure the memory has ECC too.

SDRAM PH limit  Page hit limit.

Up to 60% of all read requests fall within the same page which is called a page hit. Setting the page hit limit limits the number of times this data can be read from before the data is refreshed. Refreshing the data more often will cause a small performance hit while refreshing not often enough can and will cause stability problems depending on the quality of your RAM. Over time capacitors lost their charge. If the data is not refreshed often enough data in the memory can very well be lost which most of the time will lead to a lockup.

SDRAM idle cycle limit Setting this will determine how frequently idle banks will be refreshed. Even if a bank is empty it will still be refreshed. Generally the available settings are from 0 to 8 cycles.

In Closing.

I'm currently experimenting with some RAM to try and give you a good idea of how these various settings affect your systems performance. If you have any other timings on your board that you'd like more information on please post in this thread and I'll try to get this article updated with any other timings you want to know about.


Written By: Martin
Date: 2-29-04
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